module CLK_DIV (
    input  wire clk,
    input  wire rst_n,

    input  wire[31:0] div,
    output wire       clk_out,
    output reg        locked  
);

reg[31:0] counter;
wire       t1;
wire       c0;

BUFIO BUFIO_inst(
    .I(co),
    .O(clk_out)
);

BUFR #(
    .BUFR_DIVIDE("4"),
    .SIM_DEVICE("7SERIES")
)b1(
    .O(t1),
    .CE(1),
    .CLR(~rst_n),
    .I(clk)
);

BUFR #(
    .BUFR_DIVIDE("4"),
    .SIM_DEVICE("7SERIES")
)b2(
    .O(c0),
    .CE(1),
    .CLR(~rst_n),
    .I(t1)
);
/*
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        counter <= 0;
        locked <= 0;
        co <= 0;
    end else begin
        if (counter > div) begin
            co <= ~co;
            locked <= 1;
            counter <= 0;
        end else begin
            co <= co;
            locked <= locked;
            counter <= counter + 1;
        end
    end
end
*/
endmodule //CLK_DIV